one way of overcoming this problem is to incorporate logic circuitry . 解决这个问题的方法之一是引入逻辑电路。
binary logic circuitry, on the other hand, has only two states, logic 0 and logic 1, and noire immunity of hundreds or thousands of millvolts 另一方面,二进制逻辑电路只有两个稳态??逻辑0和逻辑1,其噪声容限可以达到数百至数千毫伏。
in addition to the dram array, the logic circuitry with the body-bias-controlled soi transistors has been developed for high-speed operation . combine some new techniques for power reduction and our dram array, we design a new low-power soi cmos dram structure and study the performance of our circuits . the results we got in the simulation and test are valuable 第三种,为了简化soi材料的电学性能测试结构,使它的测试,分析,计算摘要与传统的mos模型相兼容,我们通过引入一个耦合因子,将传统的mos模型的测试方法,公式引入soi材料的cv,i刁测试过程。